1. Technical Field
The present invention relates to a control circuit which controls a light-emitting element.
2. Background Art
There is being developed an illumination system which uses a light-emitting diode (LED) as a light-emitting element for illumination.
FIG. 4 shows a control circuit 100 of an illumination system in the related art. The control circuit 100 comprises a rectifying unit 10, a choke coil 14, a regenerative diode 16, a switching element 18, a first comparator 20, a latch unit 22, a buffer element 24, a second comparator 26, and a NOT element 28. FIG. 5 is a timing chart showing the control of the illumination system performed by the control circuit 100.
When an alternating current (AC) power supply is supplied to the rectifying unit 10, the AC power supply is full-wave rectified. The full-wave rectified voltage is supplied to an anode terminal of an LED 102 as a drive voltage. A cathode of the LED 102 is grounded through a series connection of the choke coil 14, the switching element 18, and a resistor element R1. Switching of the switching element 18 is controlled by a controller so that a current is supplied to the LED 102 through the choke coil 14, the switching element 18, and the resistor element R1, and light is emitted from the LED 102. In addition, the regenerative diode 16 which regenerates the energy stored in the choke coil 14 to the LED 102 when the switching element 18 is switched OFF is provided in parallel to the LED 102 and the choke coil 14.
A clock generator comprises the second comparator 26 and the NOT element 28. When a voltage V+ which is input to a non-inverting input terminal (+) of the second comparator 26 is higher than a voltage V− which is input to the inverted input terminal (−), an output of the second comparator 26 is at a high level (H). In this case, an output of the NOT element 28 is at a low level (L). The output of the NOT element 28 is applied to a gate terminal of a transistor Tr1, and the output of the second comparator 26 is applied to a gate terminal of a transistor Tr2. Therefore, when the output of the second comparator 26 is at the high level (H) and the output of the NOT element 28 is at the low level (L), the transistor Tr1 is set to the OFF state and the transistor Tr2 is set to the ON state, and a voltage VL is applied as the voltage V− of the inverted input terminal of the second comparator 26. In addition, the output of the second comparator 26 is applied to gate terminals of transistors Tr3 and Tr4. Therefore, when the output of the second comparator 26 is at the high level (H), the transistor Tr3 is set to the OFF state and the transistor Tr4 is set to the ON state. The charges stored in a capacitor C1 are discharged by a current source 12, and a terminal voltage of the capacitor C1; that is, the voltage V+ which is input to the non-inverting input terminal of the second comparator 26, is gradually reduced.
When the terminal voltage of the capacitor C1; that is, the voltage V+ which is input to the non-inverting input terminal of the second comparator 26, is reduced to a voltage lower than the voltage VL which is input to the inverted input terminal of the second comparator 26, the output of the second comparator 26 is switched from the high level (H) to the low level (L).
In this process, the output of the NOT element 28 is at the high level (H). When the output of the second comparator 26 is at the low level (L) and the output of the NOT element 28 is at the high level (H), the transistor Tr1 is set to the ON state and the transistor Tr2 is set to the OFF state, and the voltage V− of the inverted input terminal of the second comparator 26 is at a voltage VH which is higher than the voltage VL. In addition, when the output of the second comparator 26 is at the low level (L), the transistor Tr3 is set to the ON state and the transistor Tr4 is set to the OFF state. The capacitor C1 is charged by a current source I1, and the terminal voltage of the capacitor C1; that is, the voltage V+ which is input to the non-inverting input terminal of the second comparator 26, is gradually increased.
By repeating these operations, the clock generator generates and outputs a clock signal CLK which rises in a pulse shape at a constant period. The latch unit 22 comprises an SR latch circuit. The latch unit 22 receives the clock signal CLK at a set terminal S, and sets an output signal Q to the high level (H) when the clock signal CLK rises. The output signal Q is applied to a gate terminal of the switching element 18 through the buffer element 24, the switching element 18 is switched ON at timing when the pulse of the clock signal CLK rises, and current flows to the LED 102.
Meanwhile, to the first comparator 20, there are input a comparison voltage CS which is generated at both terminals of the resistor element R1 by the current flowing to the LED 102 and a constant reference voltage REF. An output of the first comparator 20 is input to a reset terminal R of the latch unit 22. The first comparator 20 outputs a low level (L) when the comparison voltage CS is lower than the reference voltage REF. In this case, the latch unit 22 maintains a current state, and the current flowing to the LED 102 is increased. The output of the first comparator 20 is switched to the high level (H) at timing when the comparison voltage CS becomes larger than the reference voltage REF. With this process, the latch unit 22 is reset, the switching element 18 is switched OFF, and the current to the LED 102 is stopped. In this manner, the current flowing to the LED 102 can be controlled, and an average light-emission intensity of the LED 102 can be controlled.
When the light-emitting element is operated at a fixed clock frequency using the control circuit 100 of the light-emitting element as shown in FIG. 4, a spike noise occurs in a frequency band near the clock frequency, and there may be generated an electromagnetic noise (EMI) which exceeds a standard value necessary as the control circuit 100.